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68 lines
2.5 KiB

  1. Name counter_FSM;
  2. Partno tick;
  3. Date 7th November 2006;
  4. Revision 003;
  5. Designer Ben Francis, Sam Black, Sam Burras;
  6. Company University of Birmingham;
  7. Assembly 1;
  8. Location Earth;
  9. Device P18CV8;
  10. Format JEDEC;
  11. /**********************************************************************/
  12. /* This design uses a PEEL18CV8 in order to implement a 4-bit counter */
  13. /* */
  14. /* Device pin Layout ___________ */
  15. /* CLOCK |1 \/ 20| Vcc (power supply) */
  16. /* JAM_A |2 19| CLK */
  17. /* JAM_B |3 18| QA */
  18. /* JAM_C |4 17| QB */
  19. /* JAM_D |5 16| QC */
  20. /* JAM_ENABLE |6 15| QD */
  21. /* S |7 14| Z */
  22. /* R |8 13| */
  23. /* |9 12| */
  24. /* GND |10 11| */
  25. /* |___________| */
  26. /* */
  27. /**********************************************************************/
  28. /* ORDER STATEMENT */
  29. Order: CLOCK,%1,JAM_D,%1,JAM_C,%1,JAM_B,%1,JAM_A,%1,JAM_ENABLE,%2,QD,%1,QC,%1,QB,%1,QA,%1,Z;
  30. /* TEST VECTORS */
  31. Vectors:
  32. /* Allowed States */
  33. C 1 1 0 1 1 H H L H H /* 13 */
  34. C X X X X 0 H H L L L /* 12 */
  35. C X X X X 0 H L H H L /* 11 */
  36. C X X X X 0 H L L H L /* 9 */
  37. C X X X X 0 H L L L L /* 8 */
  38. C X X X X 0 L H H H L /* 7 */
  39. C X X X X 0 L H L H L /* 5 */
  40. C X X X X 0 L H L L L /* 4 */
  41. C X X X X 0 L L H L L /* 2 */
  42. C X X X X 0 H H L H H /* 13 */
  43. /* Not Allowed States */
  44. C 1 1 1 1 1 H H H H L /* 15 */
  45. C X X X X 0 H H L H H /* 13 */
  46. C 1 1 1 0 1 H H H L L /* 14 */
  47. C X X X X 0 H L H H L /* 11 */
  48. C 0 0 1 1 1 L L H H L /* 3 */
  49. C X X X X 0 H L L H L /* 9 */
  50. C 0 1 1 0 1 L H H L L /* 6 */
  51. C X X X X 0 H L L H L /* 9 */
  52. C 0 0 0 1 1 L L L H L /* 1 */
  53. C X X X X 0 H L L H L /* 9 */
  54. C 0 0 0 0 1 L L L L L /* 0 */
  55. C X X X X 0 L H H H L /* 7 */
  56. C 1 0 1 0 1 H L H L L /* 10 */
  57. C X X X X 0 L H H H L /* 7 */